Methods of protecting structure of integrated circuit from rework

ABSTRACT

The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.

TECHNICAL FIELD

The subject matter disclosed herein relates generally to methods ofprotecting a structure of an integrated circuit (IC) from rework, andmore particularly, to methods of protecting a structure of an IC withoutimpacting the critical dimension (CD) or the profile of the structure.

BACKGROUND

Multiple patterning is a common patterning technique in thesemiconductor chip manufacturing industry. Multiple patterning enableschipmakers to image integrated circuit (IC) designs at 20 nanometers(nm) and below. For 10 nm technology, double patterning is commonly usedand typically refers to a litho-etch-litho-etch (LELE) pitch-splittingprocess or a spacer technique called self-aligned double patterning(SADP). However, in the case of 7 nm technology and below, patterningtechniques other than extreme ultraviolet (EUV) lithography requiretriple or even quadruple patterning. These patterning processes caninclude litho-etch-litho-etch-litho-etch (LELELE) or self-alignedquadruple patterning (SAQP). During such multiple patterning techniques,patterns which are formed earlier are exposed to subsequent patterningsteps, such as rework, which typically introduce changes in the criticaldimension (CD) or profile of the earlier formed features.

BRIEF SUMMARY

Methods to perform rework on an integrated circuit without impactingcritical dimension or the profile of certain features are disclosed. Ina first aspect of the disclosure, a method of protecting an openingprofile of an integrated circuit from rework includes: forming a firstlayer on a second layer, at least one of the first and second layersbeing a metal-containing layer; forming one or more first openings inthe first layer, the one or more first openings defining the openingprofile of the integrated circuit and exposing a top surface of thesecond layer; selectively growing a Group VIII metal within the one ormore first openings, thereby forming one or more first plugs; formingone or more final openings in the first layer while the one or morefirst openings in the first layer are protected by the one or more firstplugs; and removing the one or more first plugs. In this first aspect ofthe disclosure, the first layer can be a metal-containing layer and thegrowing of the Group VIII metal can comprise selectively growing theGroup VIII metal on exposed sidewalls of the first openings of themetal-containing layer, or the second layer can be a metal-containinglayer and the growing of the Group VIII metal can comprise selectivelygrowing the Group VIII metal on the exposed top surface of the secondlayer within the first openings of the first layer method of protectingan opening profile of an integrated circuit from rework, the methodcomprising: forming a first layer on a second layer, at least one of thefirst and second layers being a metal-containing layer; forming one ormore first openings in the first layer, the one or more first openingsdefining the opening profile of the integrated circuit and exposing atop surface of the second layer; selectively growing a Group VIII metalwithin the one or more first openings, thereby forming one or more firstplugs; forming one or more final openings in the first layer while theone or more first openings in the first layer are protected by the oneor more first plugs; and removing the one or more first plugs.

In a second aspect of the disclosure, a method of protecting an openingprofile of an integrated circuit from rework includes: forming a firstlayer on a second layer, the first or second layer being a titaniumnitride (TiN) layer; forming an over-layer stack on the first layer, theover-layer stack comprising a resist layer having one or more resistopenings; forming one or more first openings through the first layer atthe one or more resist openings, the one or more first openings definingthe opening profile of the integrated circuit, and exposing the topsurface of the second layer; removing at least a portion of theover-layer stack; selectively growing cobalt (Co) or ruthenium (Ru)within the one or more first openings, thereby forming one or more firstplugs; removing any remaining portion of the over-layer stack; formingone or more final openings in the first layer in the first layer whilethe one or more first openings in the first layer are protected by theone or more first plugs; and removing the one or more first plugs.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this disclosure will be more readilyunderstood from the following detailed description of the variousaspects of the disclosure taken in conjunction with the accompanyingfigures that depict various embodiments of the disclosure.

FIG. 1 shows a cross-sectional view of a multiple layer formation of aportion of an IC to have via openings patterned therein.

FIG. 2 shows a cross-sectional view of formation of first via openingsthrough an over-layer stack and into a first (metal-containing) layer.

FIG. 3 shows a cross-sectional view of selective growth of a Group VIIImetal on exposed surfaces of the first (metal-containing) layer to formfirst plugs.

FIG. 4 shows a cross-sectional view of above-plug layer stripping.

FIG. 5 shows a cross-sectional view of formation of a second over-layerstack on the plug-containing layer.

FIG. 6 shows a cross-sectional view of formation of second via openingsthrough the second over-layer stack and into the first(metal-containing) layer.

FIG. 7 shows a cross-sectional view of formation of second plugs.

FIG. 8 shows a cross-sectional view of above-plug layer stripping.

FIG. 9 shows a cross-sectional view of formation of final via openingsin the first (metal-containing) layer.

FIG. 10 shows a cross-sectional view of removal of all plugs.

FIG. 11 shows a cross-sectional view of the multiple layer formation ofa portion of an IC to have line trenches patterned therein.

FIG. 12 shows a cross-sectional view of formation of first line trenchesinto a first (silicon dioxide precursor) layer and exposure of a topsurface of a second (metal-containing) layer.

FIG. 13 shows a cross-sectional view of selective growth of a Group VIIImetal on exposed surfaces of the second (metal-containing) layer to formfirst plugs.

FIG. 14 shows a cross-sectional view of formation of a second over-layerstack on the plug-containing layer.

FIG. 15 shows a cross-sectional view of formation of second linetrenches into the first (silicon dioxide precursor) layer and exposureof the top surface of the second (metal-containing) layer.

FIG. 16 shows a cross-sectional view of selective growth of the GroupVIII metal on exposed surfaces of the second (metal-containing) layer toform second o plugs.

FIG. 17 shows a cross-sectional view of formation of final line trenchesin the first (silicon dioxide precursor) layer.

FIG. 18 shows a cross-sectional view of removal of all plugs.

It is noted that the figures of the disclosure are not necessarily toscale. The figures are intended to depict only typical aspects of thedisclosure, and therefore should not be considered as limiting the scopeof the disclosure. In the figures, like numbering represents likeelements between the figures.

DETAILED DESCRIPTION

Detailed embodiments of the claimed methods are disclosed herein;however, it can be understood that the disclosed embodiments are merelyillustrative of the claimed methods that may be embodied in variousforms. The subject matter of this disclosure may, however, be embodiedin many different forms and should not be construed as limited to theexemplary embodiments set forth herein. Rather, these exemplaryembodiments are provided so that this disclosure will be thorough andcomplete and will fully convey the scope of this disclosure to thoseskilled in the art.

In the interest of not obscuring the presentation of embodiments of thepresent disclosure, in the following detailed description, someprocessing steps or operations that are known in the art may have beencombined together for presentation and for illustration purposes and, insome instances, may have not been described in detail. In otherinstances, some processing steps or operations that are known in the artmay not be described at all. It should be understood that the followingdescription is rather focused on the distinctive features or elements ofvarious embodiments of the present disclosure.

The present disclosure relates generally to methods of protecting astructure of an integrated circuit (IC) from rework, and moreparticularly, to methods of protecting a structure of an IC withoutimpacting the critical dimension (CD) or the profile of the structure.As mentioned above, during conventional multiple patterning techniques,patterns which are formed earlier are exposed to subsequent patterningsteps, such as rework, and this typically introduces changes in the CDor profile of the earlier formed features/structures. Methods ofprotecting a structure of an IC from rework's impact on the CD orprofile of the structure are described below and with reference to theFigures.

A first embodiment of the first aspect of the disclosure is drawn towardvia patterning and is described below with respect to FIG. 1 throughFIG. 10.

FIG. 1 illustrates a multiple stack layer configuration that is to bethe subject of via patterning. From the top down, the multiple stacklayer configuration includes an over-layer stack 40, a firstmetal-containing layer 10, a second layer 20, and an under-layer stack30. First metal-containing layer 10 can contain any metal, for example,titanium. First metal-containing layer 10 can be, for instance, titaniumnitride (TiN). First metal-containing layer 10 can have a thickness inthe range of about 5 nanometers to about 50 nanometers, for instance 20nanometers. Second layer 20 can be, for example, a low-temperature oxide(LTO) layer. Second layer 20 can have a thickness in the range of about5 nanometers to about 50 nanometers, for instance, 30 nanometers.Under-layer stack 30 and over-layer stack 40 can have any number oflayers varying from one layer to two, three, four, five, etc. layers.Both of stacks 30 and 40 do not need to be present. Layers and/ormaterials below the configuration depicted in FIG. 1 (not shown) arethose such as, for example, a semiconductor substrate including forinstance a semiconductor material, front end of the line features suchas transistors, and back end of the line wiring layers.

ICs are composed of many overlapping layers. For instance, some layersof an IC include where various dopants are diffused into a substrate(typically called diffusion layers), some define where additional ionsare implanted (typically called implant layers), some define theconductors (for example, polysilicon or metal layers), and some definethe connections between the conducting layers (for example, via orcontact layers). Each IC is constructed from a specific combination ofthese types of layers and more. Under-layer stack 30 of the disclosurecan represent any combinations of layers typical for an IC. Stacks 30and 40 of the disclosure may be formed by any conventional stack(multiple layer) formation method, for example deposition. “Deposition”or “depositing” may include any now known or later developed techniquesappropriate for the material to be deposited including but not limitedto, for example: chemical vapor deposition (CVD), low-pressure CVD(LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD), highdensity plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-highvacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD),metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition,electron beam deposition, laser assisted deposition, thermal oxidation,thermal nitridation, spin-on methods, physical vapor deposition (PVD),atomic layer deposition (ALD), chemical oxidation, molecular beamepitaxy (MBE), plating, and evaporation.

In the instance of FIG. 1, under-layer stack 30 is shown as including acombination of seven layers, i.e., layers 31 through 37. The number oflayers in stack 30 is not critical and, as stated above, may vary fromone layer to two, three, four, five, etc. layers. The seven layers ofunder-layer stack 30 can include, for example, a nitrogen-doped siliconcarbide layer 31, an octamethyl cyclotetrasiloxane (OMCTS) layer 32, anOMCTS hardmask (OMCTS-HM) layer 33, a lower tetraethyl orthosilicate(TEOS) layer 34, a second metal-containing layer 35, an upper TEOS layer36, and an organic planarization layer (OPL) 37. These are just examplesof some types of layers that can be included in under-layer stack 30.Any conventional layers for an under-layer stack can be used. Secondmetal-containing layer 35 may be the same as or different than firstmetal-containing layer 10, i.e., in terms of dielectric material used.Second metal-containing layer 35 can contain any metal, for example,titanium. Second metal-containing layer 35 can be, for instance,titanium nitride (TiN).

As also depicted in FIG. 1, second metal-containing layer 35 and upperand lower TEOS layers 34, 36 have a pattern therein which is filled bythe layer above TEOS layer 36, namely organic planarization layer (OPL)layer 37. OPL 37 can have a thickness in the range of about 50nanometers to about 400 nanometers. It is noted here that conventionalmultiple patterning techniques do not typically utilize a combination offirst metal-containing layer 10 over second layer 20 (LTO) which is overOPL 37.

Also in the instance of FIG. 1, a first over-layer stack 40 is shown asincluding three layers, namely a silicon-containing anti-reflectivecoating (SiARC) layer 42 over an OPL 41 and a resist layer 43 over SiARClayer 42. SiARC layer 42 can have a thickness in the range of about 5nanometers to about 30 nanometers, for instance, 20 nanometers. OPL 41can be the same as or different from OPL 37 of under-layer stack 30. OPL41 can have a thickness in the range of about 50 nanometers to about 400nanometers, for instance 200 nanometers. Resist layer 43 can have athickness in the range of about 20 nanometers to about 100 nanometers,for instance, 50 nanometers.

The summation of stacked layers in FIG. 1 is an example configurationthat can be the subject of multiple patterning, for instance viapatterning. Before the via patterning method of the disclosure begins,one or more resist openings 44 are formed in resist layer 43.

FIG. 2 illustrates: (i) formation of one or more first via openings 200at resist openings 44 and through first over-layer stack 40 (FIG. 1) andfirst metal-containing layer 10, stopping at second layer 20, and (ii)removal of the top two layers of stack 40, namely SiARC 42 and resist 43(FIG. 1). As shown in FIG. 2, bottom-most layer OPL 41 of stack 40remains on top of first metal-containing layer 10 such that the onlyexposed surfaces of first metal-containing layer 10 arevertical/near-vertical surfaces within via openings 200. Via openings200 can be formed by any now known or later developed via formationtechnique including, but not limited to, etching, and define an openingprofile for the IC.

Etching generally refers to the removal of material from a substrate (orstructures formed on the substrate), and is often performed with a maskin place so that material may selectively be removed from certain areasof the substrate, while leaving the material unaffected, in other areasof the substrate. There are generally two categories of etching, (i) wetetch and (ii) dry etch. Wet etch is performed with a solvent (such as anacid) which may be chosen for its ability to selectively dissolve agiven material (such as oxide), while, leaving another material (such aspolysilicon) relatively intact. This ability to selectively etch givenmaterials is fundamental to many semiconductor fabrication processes. Awet etch will generally etch a homogeneous material (e.g., oxide)isotropically, but a wet etch may also etch single-crystal materials(e.g. silicon wafers) anisotropically. Dry etch may be performed using aplasma. Plasma systems can operate in several modes by adjusting theparameters of the plasma. Ordinary plasma etching produces energeticfree radicals, neutrally charged, that react at the surface of thewafer. Since neutral particles attack the wafer from all angles, thisprocess is isotropic. Ion milling, or sputter etching, bombards thewafer with energetic ions of noble gases which approach the waferapproximately from one direction, and therefore this process is highlyanisotropic. Reactive-ion etching (RIE) operates under conditionsintermediate between sputter and plasma etching and may be used toproduce deep, narrow features, such as STI trenches. In one example, RIEmay be employed for FIG. 2.

FIG. 3 illustrates formation of first plugs 300 within first viaopenings 200. First plugs 300 are formed by selective growth of a GroupVIII metal on the above-noted exposed vertical/near-vertical surfaces ofmetal-containing layer 10 within via openings 200 (FIG. 2). Group VIIImetals include iron, cobalt, nickel, ruthenium, rhodium, palladium,osmium, iridium, platinum, hassium, meitnerium and darmstadtium. TheGroup VIII metal of first plugs 300 may be any Group VIII metal such as,for example, cobalt (Co) or ruthenium (Ru). The selective growth of theGroup VIII metal can be, for example, via deposition, for instance ALD.The growth of the Group VIII metal includes a lateral growth from theexposed surfaces of metal-containing layer 10 (i.e., from exposedsidewalls of openings 200 in layer 10). The lateral growth from adjacentexposed vertical surfaces (sidewalls) within a given via opening 200ultimately joins together to form one cohesive plug 300 per via opening200 (FIG. 2). In other words, the Group VIII metal grows from a leftvertical face (sidewall) toward a right vertical face (sidewall) andalso grows from a right vertical face (sidewall) toward a left verticalface (sidewall), meeting in the middle to form one cohesive plug. Twoplugs 300 are depicted in FIG. 3, however this number may vary dependingon how many vias are desired.

FIG. 4 illustrates removal of the bottom-most layer of over-layer stack40, namely OPL 41 (FIG. 3). Any now known or later developed removaltechnique can be used so long as it is selective to the layer beingremoved and does not harm or alter metal-containing layer 10 and plugs300.

FIG. 5 through FIG. 8 show a second via patterning on the same multiplestack layer configuration that the first via openings were formed in.The steps of FIG. 5 through FIG. 8 parallel those of FIG. 1 through FIG.4, respectively. As will become evident, first plugs 300 in first viaopenings 200 will protect the CD and profile of via openings 200 duringformation of additional via openings in the situation that additionalvia openings need to be reworked.

FIG. 5 illustrates formation of a second over-layer stack 500 on firstmetal-containing layer 10 and a top surface of first plugs 300. Secondoverl-layer stack 500 is shown as including three layers, namely asilicon-containing anti-reflective coating (SiARC) layer 502 over an OPL501 and a resist layer 503 over SiARC layer 502. Similar to FIG. 1, oneor more second resist openings 504 are formed in resist layer 503.

FIG. 6 illustrates: (i) formation of second via openings 600 at resistopenings 504 and through second over-layer stack 500 (FIG. 5) and firstmetal-containing layer 10, stopping at second layer 20, and (ii) removalof the top two layers of stack 500, namely SiARC 502 and resist 503(FIG. 5). Similar to FIG. 2, bottom-most layer OPL 501 of over-layerstack 500 remains on top of first metal-containing layer 10 such thatthe only exposed surfaces of first metal-containing layer 10 arevertical/near-vertical surfaces (sidewalls) within via openings 600. Viaopenings 600 can be formed by any now known or later developed viaformation technique including, but not limited to, etching. Second viaopenings 600 can be formed by the same or different technique as that offirst via openings 200, and can add to the opening profile of the IC.

FIG. 7 illustrates formation of second plugs 700 within second viaopenings 600 (FIG. 6). Second plugs 700 are formed by selective growthof a Group VIII metal on the exposed vertical/near-vertical surfaces offirst metal-containing layer 10 within via openings 600 (FIG. 6). Sameas for first plugs 300, the growth of the Group VIII metal is a lateralgrowth from the exposed surfaces of metal-containing layer 10. Thelateral growth from adjacent exposed vertical surfaces (sidewalls)within a given via opening 600 ultimately joins together to form onecohesive plug 700 per via opening 600. Two plugs 700 are depicted inFIG. 7, however this number may vary depending on how many vias aredesired.

FIG. 8 depicts the result of removal of the bottom-most layer ofover-layer stack 500, namely OPL 501, as shown in FIG. 7. Any now knownor later developed removal technique can be used so long as it isselective to the layer being removed and does not harm or alter firstmetal-containing layer 10 and plugs 300, 700.

FIG. 9 and FIG. 10 show a final (third) via patterning on the samemultiple stack layer configuration that the first and second viaopenings were formed in. As will become evident, first plugs 300 andsecond plugs 700 (FIG. 8) in first and second via openings 200 and 600,respectively (FIG. 2, FIG. 6), will protect the CD and profile of viaopenings 200, 600 (FIG. 2, FIG. 6) during formation of the final (third)via openings in the situation that the final (third) via openings needto be reworked.

FIG. 9 illustrates formation of final (third) via openings 900 in firstmetal-containing layer 10. Via openings 900 can be formed by any nowknown or later developed via formation technique including, but notlimited to, etching. Final (third) via openings 900 can be formed by thesame or different technique as that of first via openings 200 and/orsecond via openings 600. Since via openings 900 are the final viaopenings being patterned in this example, there is no need for plugformation within via openings 900.

FIG. 10 illustrates removal of all plugs, namely first plugs 300 andsecond plugs 700. Such removal of the Group VIII metal that the plugsare made of can be performed with deionized water, thus it is safe anddoes not impact first metal-containing layer 10 and second layer 20.

The method as depicted in FIG. 1 through FIG. 10 results in multiple viapatterning wherein the CD and profile of prior formed via openings areunchanged by the subsequent forming of additional via openings, i.e.,the opening profile of the IC is protected. For example, the CD andprofile of first via openings 200 are unchanged by the forming of secondvia openings 600 and third/final via openings 900, and second viaopenings 600 are unchanged by the forming of third/final via openings900. Consequently, vias formed in via openings have their CD and profileprotected resulting in improved CD and profile uniformity amongst thevias. This improved uniformity minimizes the impact of rework on yield,for example, it minimizes degraded product yield quality due to rework.

The summation of FIG. 1 through FIG. 10 illustrates a LELELE process(triple patterning); however, the method of the disclosure can beequally applied to doubling patterning (e.g., LELE) or quadruplepatterning and beyond. Regardless of the degree of multiple patterning(e.g., double, triple, quadruple, etc.), the negative impact that reworkcan have on product yield quality can be minimized.

A second embodiment of the first aspect of the disclosure is drawntoward line patterning and is described below with respect to FIG. 11through FIG. 18.

FIG. 11 illustrates a multiple stack layer configuration that is to bethe subject of line patterning. The multiple stack layer configurationincludes a first layer 110 on a second (metal-containing) layer 120,second (metal-containing) layer having an under-layer stack 130thereunder, and first layer 110 having an over-layer stack 140thereover. Second metal-containing layer 120 can contain any metal, forexample, titanium. Second metal-containing layer 120 can be, forinstance, titanium nitride (TiN). Second metal-containing layer 120 canhave a thickness in the range of about 5 nanometers to about 50nanometers, for instance 20 nanometers. First layer 110 can be, forexample, a silicon dioxide (SiO₂) precursor layer which in turn can be,for example, TEOS. First layer 110 can have a thickness in the range ofabout 5 nanometers to about 50 nanometers, for instance 20 nanometers.The number of layers in under-layer stack 130 and over-layer stack 140is not critical and may vary from one layer to two, three, four, five,etc. layers. Layers and/or materials below the configuration depicted inFIG. 11 (not shown) are those such as, for example, a semiconductorsubstrate including for instance a semiconductor material, front end ofthe line features such as transistors, and back end of the line wiringlayers.

In the instance of FIG. 11, under-layer stack 130 is shown as includingthree layers, namely an octamethyl cyclotetrasiloxane (OMCTS) layer 132over a nitrogen-doped silicon carbide layer 131, and an OMCTS hardmask(OMCTS-HM) layer 133 over OMCTS layer 132. These are just examples ofsome types of layers that can be included in under-layer stack 130. Anyconventional layers for an under-layer stack can be used.

Also in the instance of FIG. 11 and similar to FIG. 1, a firstover-layer stack 140 is shown as including three layers, namely aSi-containing anti-reflective coating (SiARC) layer 142 over an OPL 141and a resist layer 143 over SiARC layer 142. SiARC layer 142 can have athickness in the range of about 5 nanometers to about 30 nanometers, forinstance, 20 nanometers. OPL 141 can have a thickness in the range ofabout 50 nanometers to about 400 nanometers, for instance 200nanometers. Resist layer 143 can have a thickness in the range of about20 nanometers to about 100 nanometers, for instance, 50 nanometers.

The summation of stacked layers in FIG. 11 is an example configurationthat can be the subject of multiple patterning, for instance, linepatterning. Before the line patterning method of the disclosure begins,one or more resist openings 144 are formed in resist layer 143.

FIG. 12 illustrates: (i) formation of one or more first line trenches1200 at resist openings 144 and through over-layer stack 140 and firstlayer 110 (FIG. 11), stopping at second metal-containing layer 120, and(ii) removal of over-layer stack 140 (FIG. 11). As shown in FIG. 12, theonly exposed surfaces of second metal-containing layer 120 are a topsurface of second metal-containing layer 120 within each line trench1200. Line trenches 1200 can be formed by any now known or laterdeveloped line trench formation technique including, but not limited to,etching, and define an opening profile for the IC.

FIG. 13 illustrates formation of first plugs 1300 within first linetrenches 1200 (FIG. 12). First plugs 1300 are formed by selective growthof a Group VIII metal on the above-noted exposed top surfaces of secondmetal-containing layer 120 within line trenches 1200 (FIG. 12). GroupVIII metals are described above with respect to the first embodiment ofthis aspect of the disclosure. The Group VIII metal of first plugs 1300may be any Group VIII metal such as, for example, Co or Ru. Theselective growth of the Group VIII metal can be for example, viadeposition, for instance ALD. The growth of the Group VIII metalincludes an upward growth from the exposed top surfaces of secondmetal-containing layer 120. The upward growth continues for thethickness of first layer 110 and forms one plug 1300 per line trench1200. Two plugs 1300 are depicted in FIG. 13, however this number mayvary depending on how many lines are desired.

FIG. 14 through FIG. 16 show a second line patterning on the samemultiple stack layer configuration that the first line trenches wereformed in. The steps of FIG. 14 through FIG. 16 parallel those of FIG.11 through FIG. 13, respectively. As will become evident, first plugs1300 in first line trenches 1200 will protect the CD and profile of linetrenches 1200 during formation of additional line trenches in thesituation that additional line trenches need to be reworked.

FIG. 14 illustrates formation of a second over-layer stack 1150 on firstlayer 110 and a top surface of first plugs 1300 (FIG. 13). Secondover-layer stack 1150 is shown as including three layers, namely aSi-containing anti-reflective coating (SiARC) layer 1152 over an OPL1151 and a resist layer 1153 over SiARC layer 1152. Similar to FIG. 11,one or more second resist openings 1154 are formed in resist layer 1153.

FIG. 15 illustrates: (i) formation of one or more second line trenches1500 at resist openings 1154 and through over-layer stack 1150 and firstlayer 110 (FIG. 14), stopping at second metal-containing layer 120, and(ii) removal of over-layer stack 1150 (FIG. 14). As shown in FIG. 15,the only exposed surfaces of second metal-containing layer 120 are a topsurface of second metal-containing layer 120 within each line trench1500. Line trenches 1500 can be formed by any now known or laterdeveloped line trench formation technique including, but not limited to,etching. Line trenches 1500 can be formed by the same or differenttechnique as that of line trenches 1200, and add to the opening profileof the IC.

FIG. 16 illustrates formation of second plugs 1600 within second linetrenches 1500 (FIG. 15). Second plugs 1600 are formed by selectivegrowth of a Group VIII metal on the exposed top surfaces of secondmetal-containing layer 120 within second line trenches 1500. Same as forfirst plugs 1300, the growth of the Group VIII metal is an upward growthfrom the exposed top surfaces of second metal-containing layer 120. Theupward growth continues for the thickness of first layer 110 and formsone plug 1600 per line 1500 (FIG. 15). Two plugs 1600 are depicted inFIG. 16, however this number may vary depending on how many lines aredesired.

FIG. 17 and FIG. 18 show a final (third) line patterning on the samemultiple stack layer configuration that the first and second linetrenches were formed in. As will become evident, first plugs 1300 andsecond plugs 1600 in first and second line trenches 1200 and 1500,respectively (FIG. 12, FIG. 15), will protect the CD and profile of linetrenches 1200, 1500 (FIG. 12, FIG. 15) during formation of the final(third) line trenches in the situation that the final (third) linetrenches need to be reworked.

FIG. 17 illustrates formation of final (third) line trenches 1700 infirst layer 110. Line trenches 1700 can be formed by any now known orlater developed line trench formation technique including, but notlimited to, etching. Final (third) line trenches 1700 can be formed bythe same or different technique as that of first line trenches 1200and/or second line trenches 1500. Since line trenches 1700 are the finalline trenches being patterned in this example, there is no need for plugformation within line trenches 1700.

FIG. 18 illustrates removal of all plugs, namely first plugs 1300 andsecond plugs 1600. Such removal of the Group VIII metal that the plugsare made of can be performed with deionized water, thus it is safe anddoes not impact first layer 110 and second metal-containing layer 120.

The method as depicted in FIG. 11 through FIG. 18 results in multipleline patterning wherein the CD and profile of prior formed line trenchesare unchanged by the subsequent forming of additional line trenches. Forexample, the CD and profile of first line trenches 1200 are unchanged bythe forming of second line trenches 1500 and third/final line trenches1700, and second line trenches 1500 are unchanged by the forming ofthird/final line trenches 1700. Consequently, lines formed in linetrenches have their CD and profile protected, resulting in improved CDand profile uniformity amongst the lines. This improved uniformityminimizes the impact of rework on yield, for example, it minimizesdegraded product yield quality due to rework.

The summation of FIG. 11 through FIG. 18 illustrates a LELELE process(triple patterning); however, the method of the disclosure can beequally applied to doubling patterning (e.g., LELE) or quadruplepatterning and beyond. Regardless of the degree of multiple patterning(e.g., double, triple, quadruple, etc.), the negative impact that reworkcan have on product yield quality can be minimized.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Approximating language, as used herein throughout the specification andclaims, may be applied to modify any quantitative representation thatcould permissibly vary without resulting in a change in the basicfunction to which it is related. Accordingly, a value modified by a termor terms, such as “about”, “approximately” and “substantially”, are notto be limited to the precise value specified. In at least someinstances, the approximating language may correspond to the precision ofan instrument for measuring the value. Here and throughout thespecification and claims, range limitations may be combined and/orinterchanged, such ranges are identified and include all the sub-rangescontained therein unless context or language indicates otherwise.“Approximately” or “about” as applied to a particular value of a rangeapplies to both values, and unless otherwise dependent on the precisionof the instrument measuring the value, may indicate +/−10% of the statedvalue(s).

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present disclosure has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the disclosure in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the disclosure. Theembodiments were chosen and described in order to best explain theprinciples of the disclosure and the practical application, and toenable others of ordinary skill in the art to understand the disclosurefor various embodiments with various modifications as are suited to theparticular use contemplated.

We claim:
 1. A method of protecting an opening profile of an integratedcircuit from rework, the method comprising: forming a first layer on asecond layer, at least one of the first and second layers being ametal-containing layer; forming one or more first openings in the firstlayer, the one or more first openings defining the opening profile ofthe integrated circuit and exposing a top surface of the second layer;selectively growing a Group VIII metal within the one or more firstopenings, thereby forming one or more first plugs; forming one or morefinal openings in the first layer while the one or more first openingsin the first layer are protected by the one or more first plugs; andremoving the one or more first plugs.
 2. The method of claim 1, whereinthe first layer is the metal-containing layer and the growing of theGroup VIII metal comprises selectively growing the Group VIII metal onexposed sidewalls of the first openings of the metal-containing layer.3. The method of claim 2, wherein the metal-containing layer is atitanium nitride (TiN) layer.
 4. The method of claim 2, wherein theGroup VIII metal is cobalt (Co) or ruthenium (Ru).
 5. The method ofclaim 2, wherein the second layer is a low-temperature oxide (LTO)layer.
 6. The method of claim 2, wherein a profile of the one or morefirst openings is unchanged by the forming of the one or more finalopenings.
 7. The method of claim 2, further comprising, after theforming of the first plugs and before the forming of the final openings:forming one or more second openings in the first layer, the secondopenings exposing the top surface of the second layer and furtherdefining the opening profile, the one or more first openings in thefirst layer and the opening profile being protected by the one or morefirst plugs; and selectively growing the Group VIII metal on exposedsidewalls of the second openings of the metal-containing layer, therebyforming one or more second plugs, wherein the removing the one or morefirst plugs also includes removing the one or more second plugs.
 8. Themethod of claim 7, wherein the first and second openings are viaopenings and the forming of the first and second via openings comprises:forming an over-layer stack on the first layer, the over-layer stackcomprising a resist layer having one or more resist openings; formingvia openings through the first layer at the one or more resist openingssuch that the top surface of the second layer is exposed; and removingthe over-layer stack.
 9. The method of claim 7, wherein a profile of theone or more first openings is unchanged by the forming of the one ormore second openings and the one or more final openings, and a profileof the one or more second openings is unchanged by the forming of theone or more final openings.
 10. The method of claim 1, wherein thesecond layer is the metal-containing layer and the growing of the GroupVIII metal comprises selectively growing the Group VIII metal on theexposed top surface of the second layer within the first openings of thefirst layer.
 11. The method of claim 10, wherein the metal-containinglayer is a titanium nitride (TiN) layer.
 12. The method of claim 10,wherein the Group VIII metal is cobalt (Co) or ruthenium (Ru).
 13. Themethod of claim 10, wherein the first layer is a silicon dioxide (SiO₂)precursor layer.
 14. The method of claim 13, wherein the SiO₂ precursorlayer comprises tetraethyl orthosilicate (TEOS).
 15. The method of claim10, wherein a profile of the one or more first openings is unchanged bythe forming of the one or more final openings.
 16. The method of claim10, further comprising, after the forming of the first plugs and beforethe forming of the final openings: forming one or more second openingsin the first layer, the second openings exposing the top surface of thesecond layer, the one or more first openings in the first layer and theopening profile being protected by the one or more first plugs; andselectively growing the Group VIII metal on the exposed top surface ofthe second layer within the second openings of the first layer, therebyforming one or more second plugs.
 17. The method of claim 16, whereinthe first and second openings are line trenches and the forming of thefirst and second line trenches comprises: forming an over-layer stack onthe first layer, the over-layer stack comprising a resist layer havingone or more resist openings; forming line trenches through the firstlayer at the one or more resist openings such that the top surface ofthe second layer is exposed; and removing the over-layer stack.
 18. Themethod of claim 16, wherein a profile of the one or more first openingsis unchanged by the forming of the one or more second openings and theone or more final openings, and a profile of the one or more secondopenings is unchanged by the forming of the one or more final openings.19. A method of protecting an opening profile of an integrated circuitfrom rework, the method comprising: forming a first layer on a secondlayer, the first or second layer being a titanium nitride (TiN) layer;forming an over-layer stack on the first layer, the over-layer stackcomprising a resist layer having one or more resist openings; formingone or more first openings through the first layer at the one or moreresist openings, the one or more first openings defining the openingprofile of the integrated circuit, and exposing the top surface of thesecond layer; removing at least a portion of the over-layer stack;selectively growing cobalt (Co) or ruthenium (Ru) within the one or morefirst openings, thereby forming one or more first plugs; removing anyremaining portion of the over-layer stack; forming one or more finalopenings in the first layer in the first layer while the one or morefirst openings in the first layer are protected by the one or more firstplugs; and removing the one or more first plugs.
 20. The method of claim19, wherein the second layer is formed over an under-layer stack, theunder-layer stack comprising one or more layers of the integratedcircuit, one or more stacks of layers of the integrated circuit, or acombination thereof.